International Science Index

2
10007795
CPU Architecture Based on Static Hardware Scheduler Engine and Multiple Pipeline Registers
Abstract:

The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

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7
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1
11124
Efficient Scheduling Algorithm for QoS Support in High Speed Downlink Packet Access Networks
Abstract:
In this paper, we propose APO, a new packet scheduling scheme with Quality of Service (QoS) support for hybrid of real and non-real time services in HSDPA networks. The APO scheduling algorithm is based on the effective channel anticipation model. In contrast to the traditional schemes, the proposed method is implemented based on a cyclic non-work-conserving discipline. Simulation results indicated that proposed scheme has good capability to maximize the channel usage efficiency in compared to another exist scheduling methods. Simulation results demonstrate the effectiveness of the proposed algorithm.
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952
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