International Science Index

4
10007795
CPU Architecture Based on Static Hardware Scheduler Engine and Multiple Pipeline Registers
Abstract:

The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Paper Detail
7
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3
10007019
Improving the Performances of the nMPRA Architecture by Implementing Specific Functions in Hardware
Abstract:

Minimizing the response time to asynchronous events in a real-time system is an important factor in increasing the speed of response and an interesting concept in designing equipment fast enough for the most demanding applications. The present article will present the results regarding the validation of the nMPRA (Multi Pipeline Register Architecture) architecture using the FPGA Virtex-7 circuit. The nMPRA concept is a hardware processor with the scheduler implemented at the processor level; this is done without affecting a possible bus communication, as is the case with the other CPU solutions. The implementation of static or dynamic scheduling operations in hardware and the improvement of handling interrupts and events by the real-time executive described in the present article represent a key solution for eliminating the overhead of the operating system functions. The nMPRA processor is capable of executing a preemptive scheduling, using various algorithms without a software scheduler. Therefore, we have also presented various scheduling methods and algorithms used in scheduling the real-time tasks.

Paper Detail
79
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2
3970
Stochastic Scheduling to Minimize Expected Lateness in Multiple Identical Machines
Abstract:
There are many real world problems in which parameters like the arrival time of new jobs, failure of resources, and completion time of jobs change continuously. This paper tackles the problem of scheduling jobs with random due dates on multiple identical machines in a stochastic environment. First to assign jobs to different machine centers LPT scheduling methods have been used, after that the particular sequence of jobs to be processed on the machine have been found using simple stochastic techniques. The performance parameter under consideration has been the maximum lateness concerning the stochastic due dates which are independent and exponentially distributed. At the end a relevant problem has been solved using the techniques in the paper..
Paper Detail
748
downloads
1
11124
Efficient Scheduling Algorithm for QoS Support in High Speed Downlink Packet Access Networks
Abstract:
In this paper, we propose APO, a new packet scheduling scheme with Quality of Service (QoS) support for hybrid of real and non-real time services in HSDPA networks. The APO scheduling algorithm is based on the effective channel anticipation model. In contrast to the traditional schemes, the proposed method is implemented based on a cyclic non-work-conserving discipline. Simulation results indicated that proposed scheme has good capability to maximize the channel usage efficiency in compared to another exist scheduling methods. Simulation results demonstrate the effectiveness of the proposed algorithm.
Paper Detail
952
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