International Science Index
Investigation of Threshold Voltage Shift in Gamma Irradiated N-Channel and P-Channel MOS Transistors of CD4007
The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from ID-VG characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.
A Fault-Tolerant Full Adder in Double Pass CMOS Transistor
This paper presents a fault-tolerant implementation for
adder schemes using the dual duplication code. To prove the
efficiency of the proposed method, the circuit is simulated in double
pass transistor CMOS 32nm technology and some transient faults are
voluntary injected in the Layout of the circuit. This fully differential
implementation requires only 20 transistors which mean that the
proposed design involves 28.57% saving in transistor count
compared to standard CMOS technology.
Comparative Performance Analysis of Nonlinearity Cancellation Techniques for MOS-C Realization in Integrator Circuits
In this paper, a comparative performance analysis of
mostly used four nonlinearity cancellation techniques used to realize
the passive resistor by MOS transistors, is presented. The comparison
is done by using an integrator circuit which is employing sequentially
Op-amp, OTRA and ICCII as active element. All of the circuits are
implemented by MOS-C realization and simulated by PSPICE
program using 0.35μm process TSMC MOSIS model parameters.
With MOS-C realization, the circuits became electronically tunable
and fully integrable which is very important in IC design. The output
waveforms, frequency responses, THD analysis results and features
of the nonlinearity cancellation techniques are also given.
Practical Simulation Model of Floating-Gate MOS Transistor in Sub 100nm Technologies
As the Silicon oxide scaled down in MOSFET
technology to few nanometers, gate Direct Tunneling (DT) in
Floating gate (FGMOSFET) devices has become a major concern for
analog designers. FGMOSFET has been used in many low-voltage
and low-power applications, however, there is no accurate model that
account for DT gate leakage in nano-scale. This paper studied and
analyzed different simulation models for FGMOSFET using TSMC
90-nm technology. The simulation results for FGMOSFET cascade
current mirror shows the impact of DT on circuit performance in
terms of current and voltage without the need for fabrication. This
works shows the significance of using an accurate model for
FGMOSFET in nan-scale technologies.
Design and Realization of an Electronic Load for a PEM Fuel Cell
In order to further understand the behavior of PEM fuel cell and optimize their performance, it is necessary to perform measurements in real time. The internal impedance measurement by electrochemical impedance spectroscopy (EIS) is of great importance. In this work, we present the impedance measurement method of a PEM fuel cell by electrochemical impedance spectroscopy method and the realization steps of electronic load for this measuring technique implementation. The theoretical results are obtained from the simulation of software PSPICE® and experimental tests are carried out using the Ballard Nexa™ PEM fuel cell system.
Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime
Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.
A Novel Logarithmic Current-Controlled Current Amplifier (LCCA)
A new OTA-based logarithmic-control variable gain
current amplifier (LCCA) is presented. It consists of two Operational
Transconductance Amplifier (OTA) and two PMOS transistors
biased in weak inversion region. The circuit operates from 0.6V DC
power supply and consumes 0.6 μW. The linear-dB controllable
output range is 43 dB with maximum error less than 0.5dB. The
functionality of the proposed design was confirmed using HSPICE in
0.35μm CMOS process technology.
A Low Power High Frequency CMOS RF Four Quadrant Analog Mixer
This paper describes a CMOS four-quadrant
multiplier intended for use in the front-end receiver by utilizing the
square-law characteristic of the MOS transistor in the saturation
region. The circuit is based on 0.35 um CMOS technology simulated
using HSPICE software. The mixer has a third-order inter the power
consumption is 271uW from a single 1.2V power supply. One of the
features of the proposed design is using two MOS transistors
limitation to reduce the supply voltage, which leads to reduce the
power consumption. This technique provides a GHz bandwidth
response and low power consumption.
A Low-Voltage Current-Mode Wheatstone Bridge using CMOS Transistors
This paper presents a new circuit arrangement for a
current-mode Wheatstone bridge that is suitable for low-voltage
integrated circuits implementation. Compared to the other proposed
circuits, this circuit features severe reduction of the elements number,
low supply voltage (1V) and low power consumption (
Effect of Low Frequency Memory on High Power 12W LDMOS Transistors Intermodulation Distortion
The increasing demand for higher data rates in wireless communication systems has led to the more effective and efficient use of all allocated frequency bands. In order to use the whole bandwidth at maximum efficiency, one needs to have RF power amplifiers with a higher linear level and memory-less performance. This is considered to be a major challenge to circuit designers. In this thesis the linearity and memory are studied and examined via the behavior of the intermodulation distortion (IMD). A major source of the in-band distortion can be shown to be influenced by the out-of-band impedances presented at either the input or the output of the device, especially those impedances terminated the low frequency (IF) components. Thus, in order to regulate the in-band distortion, the out of-band distortion must be controllable. These investigations are performed on a 12W LDMOS device characterised at 2.1 GHz within a purpose built, high-power measurement system.
Design of Folded Cascode OTA in Different Regions of Operation through gm/ID Methodology
This paper presents an optimized methodology to
folded cascode operational transconductance amplifier (OTA) design.
The design is done in different regions of operation, weak inversion,
strong inversion and moderate inversion using the gm/ID methodology
in order to optimize MOS transistor sizing.
Using 0.35μm CMOS process, the designed folded cascode OTA
achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz
in strong inversion mode. In moderate inversion mode, it has a 92dB
DC gain and provides a gain bandwidth product of around 69MHz.
The OTA circuit has a DC gain of 75.5dB and unity-gain frequency
limited to 19.14MHZ in weak inversion region.
Versatile Dual-Mode Class-AB Four-Quadrant Analog Multiplier
Versatile dual-mode class-AB CMOS four-quadrant
analog multiplier circuit is presented. The dual translinear loops and
current mirrors are the basic building blocks in realization scheme.
This technique provides; wide dynamic range, wide-bandwidth response
and low power consumption. The major advantages of this
approach are; its has single ended inputs; since its input is dual translinear
loop operate in class-AB mode which make this multiplier
configuration interesting for low-power applications; current multiplying,
voltage multiplying, or current and voltage multiplying can
be obtainable with balanced input. The simulation results of versatile
analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth
of about 19MHz, a maximum power consumption of 0.46mW,
and temperature compensated. Operation of versatile analog multiplier
was also confirmed through an experiment using CMOS transistor
A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem
Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with